EDN

Altera Quartus II Software v14.1 Enables TFLOPS Performance in Industry’s First FPGA with Hardened Floating Point DSP Blocks

Integrated IEEE 754-compliant, floating-point DSP blocks in Arria 10 FPGAs and SoCs deliver unparalleled levels of DSP performance, designer productivity and logic efficiency. The Quartus II software ...
Digit

How to Program Your First FPGA Device

This tutorial shows you how to create the hardware equivalent of “Hello World”: a blinking LED. This is a simple exercise to get you started using the Intel® Quartus® software for FPGA development.
EDN

Altera unveils Quartus II software version 8.1

The folks at Altera have unveiled their Quartus II software version 8.1 for CPLD, FPGA, and HardCopy ASIC designs. Based on internal benchmarks, the folks at Altera claim high-density FPGA compile ...
Design-Reuse

Altera Continues Its Productivity Leadership Position With Quartus II Software Version 8.1

San Jose, Calif., November 3, 2008—Reaffirming its leadership position in performance and productivity for CPLD, FPGA, and HardCopy ® ASIC designs, Altera Corporation (NASDAQ: ALTR) today unveiled ...
Electronics Weekly

Altera speeds FPGA recompile with Quartus II software

Altera has announced the release of the latest version of its Quartus II development software for CPLD, FPGA and HardCopy Asic designs. Version 10.0 of the software includes support for Altera’s 28-nm ...
New Electronics

Mouser stocks latest Quartus II software from Altera

Mouser is now offering the latest version of Altera's Quartus II software platform. Version 13.0 offers design entry, simulation, synthesis, place and route, and verification for cpld, fpga, SoC and ...